The increasing capacities and faster speeds of semiconductor memory devices including dynamic RAM are remarkable. In particular, with regard to DDR SDRAM (Double Data Rate Synchronous DRAM), internal operations are pipelined and given commands are sequentially executed by synchronizing with a clock from outside, and in addition, high speed operation of a system is realized so as to be able to perform data transfer at a rate of double the clock frequency. With the abovementioned DDR SDRAM and the like, a DLL (Delay Locked Loop) circuit is used, an internal circuit is operated by synchronizing with the clock provided from outside, and high speed data transfer is realized.
FIG. 1 is a timing diagram when a read command is executed in this DDR SDRAM. In FIG. 1, “CK” is a system clock signal provided by a memory controller to a CK terminal of the DDR SDRAM, and “/CK” is an inverted signal thereof provided to a /CK terminal. In FIG. 1, the CK signal is shown by a full line, and /CK is shown by a broken line. Furthermore “Command” indicates a command given by the memory controller to the DDR SDRAM, and “Bank Add” and “Col Add” indicate a bank address and a column address at that time. In addition, when a read command has been inputted, data outputted from a DQ terminal (data terminal) of the DDR SDRAM, and a data strobe signal outputted from a DQS terminal (data strobe terminal) are indicated by “DQ” and “DQS”. With regard to the data strobe signal, in addition to the DQS signal, a /DQS signal that is an inverted signal thereof is outputted from a /DQS terminal, but this is omitted in FIG. 1.
Furthermore, in addition to a standard DQS output signal, the drawing also shows fastest and slowest timing for when output timing of the DQS signal varies. Moreover, CAS latency is CL=6, and Additive Latency is AL=0.
In FIG. 1, first, at a rising edge at timing T0, a read command is given to the DDR SDRAM. In a standard DDR SDRAM, since a DLL is built in, phases of the system clock signals CK and /CK provided from the memory controller side, and the phase of a signal outputted from the DDR SDRAM to the DQS terminal, match. As described above, with the CAS latency CL of 6, since the additive latency AL is 0, after the DQS terminal outputs one cycle at low level as a read preamble in advance, it rises in synchronization with rising of the system clock of a sixth clock, T6. Thereafter, toggle operation is repeated in synchronization with the system clock until burst output is completed. At this time, data is outputted in synchronization with rising and falling of the DQS terminal, from the DQ terminal. Since the DQS signal outputted from the DDR SDRAM is made synchronous by a DLL circuit with the system clock signals CK and /CK provided from the memory controller side, there is little phase shift, A DQS signal line is a bidirectional signal line, with cases of output as a data strobe signal from the DDR SDRAM to the memory controller side, and cases of output as a data strobe signal from the memory controller side to the DDR SDRAM. Therefore, where data is not outputted in either type of case, there is a high impedance state, with an intermediate potential, according to a termination resistance.
Therefore, with regard to a DDR SDRAM specification, when data is outputted, prior to the data output, a low level preamble signal is outputted for a one cycle period of the CK signal. For example, as shown in FIG. 1, when the DDR SDRAM outputs read data, a read preamble signal is outputted from the DQS terminal one cycle beforehand, and this read preamble signal is received in the memory controller, and a state of waiting for the read data reception is entered.
A mismatch of falling and rising edges of the DQS terminal and the /DQS terminal of the DDR SDRAM with respect to falling and rising edges of the CK terminal and the /CK terminal is specified as tDQSCK. With a case where a value of this tDQSCK is 0 (an ideal case), as tDQSCKtyp, a minimum value of variation is indicated as tDQSCKmin, and a maximum value is indicated as tDQSCKmax. In a normal DDR SDRAM, since a DLL circuit is used and the phase of the DQS signal is matched with the system clock, there is little variation. In FIG. 1, with regard to a time-period from ts to te, the preamble signal is outputted in cases of both tDQSCKmin and tDQSCKmax. Therefore, in the memory controller, it is possible to relatively easily detect the preamble signal, and in that regard, with an average period tCKave of the system clock CK as 1875 ps, if tDQmin is −300 ps and tDQSCKmax is 300 ps, a time-period from ts to te is 1275 ps, according to Expression (1). However, in actuality, since there is a propagation delay in wiring from the DDR SDRAM to the memory controller, and a variation thereof, this type of accurate time length does not occur.1875 ps−300 ps−300 ps=1275 ps  Expression (1)
FIG. 2 is a control flow diagram of the memory controller when a read command is executed. With regard to the memory controller, after outputting a read command in step S11, and after waiting CAS latency—one cycle in step S12, a gate detecting the DQS signal is opened in step S13, and the read preamble signal is detected. If timing of opening the gate is made at a time at which a propagation delay is added to a time-period from the abovementioned is until te, even in a case where the tDQSCK varies, ideally it is possible to detect the preamble signal in one time (step S14). In a case where the preamble cannot be detected, since there is some sort of abnormality, there is a transition to abnormality processing (step S15). On the other hand, in a case where the preamble signal is normally detected, there is a transition to detection processing of a toggle edge (step S16). In a case where the toggle edge could be detected, with regard to a memory read operation, since the DQS signal and the DQ signal change at the same time, the DQ signal is taken up in an intermediate time until the next edge at which DQ signal change has become stable (step S18). An operation from the toggle edge detection of step S16 until the DQ signal of step S18 is taken up is repeated until the data is completed, and at the completion of the data, the read operation is finished (step S19). Patent Document 1 describes a circuit in which a read preamble signal is generated in the DDR SDRAM. In the abovementioned description, it is assumed throughout that the DDR SDRAM has a DDL circuit, and that the phase of the DQS output signal matches the phase of the CK signal with good accuracy.
On the other hand, there is a demand for reduction in power consumption in semiconductor memory devices, not limited to devices such as notebook PCs that operate on batteries, but also in the area of servers and the like. However, since the clock must always be operated at high speed, the DLL is a cause of power consumption increase. With regard to this, there is a description on page 37 of Non-Patent Document 1, of providing a DLL OFF mode in which the DLL is turned OFF, in a DDR3 SDRAM, which is the latest specification of the abovementioned DDR SDRAM. According to Non-Patent Document 1, there is a description that, the DLL OFF mode is used with the CAS latency CL=6, and the DQS signal when a read operation is performed is generated from a timing signal one cycle before, with regard to a DLL ON mode.    [Patent Document 1]    JP Patent Kokai Publication No. JP-P2008-198356A    [Non-Patent Document 1]    JEDEC STANDARD DDR3 SDRAM Specification, JESD79-3B, April, 2008, JEDEC Solid State Technology Association, page 37